`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:28:06 05/05/2013
// Design Name:   asynchronous_FIFO
// Module Name:   C:/Users/jboedin/Desktop/LAB3/tb/tb_asynchronous_FIFO.v
// Project Name:  LAB3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: asynchronous_FIFO
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_asynchronous_FIFO;

	// Inputs
	reg [7:0] wdata;
	reg winc;
	reg wclk;
	reg rinc;
	reg rclk;
	reg iResetb;

	// Outputs
	wire [7:0] rdata;
	wire wfull;
	wire rempty;

	// Instantiate the Unit Under Test (UUT)

asynchronous_FIFO # (
	.DSIZE(8), 
	.ASIZE(4)) uut (
	.rdata(rdata), 
	.wfull(wfull), 
	.rempty(rempty), 
	.wdata(wdata),
	.winc(winc), 
	.wclk(wclk), 
	.wrst_n(iResetb), 
	.rinc(rinc), 
	.rclk(rclk), 
	.rrst_n(iResetb)
);

	//50mhz clock
	initial begin
		rclk = 1'b0;
		forever #10 rclk = ~rclk;
	end
	
	//100mhz clock
	initial begin
		wclk = 1'b0;
		forever #5 wclk = ~wclk;
	end
	
	initial begin
		// Initialize Inputs
		wdata = 7'b10101111;
		winc = 0;
		wclk = 0;
		rinc = 0;
		rclk = 0;
		iResetb = 0;

		// Wait 100 ns for global reset to finish
		#100;
 		iResetb = 1;
       
		// Add stimulus here
		#305;
		winc = 1; #5
		winc = 0; #100
		rinc = 1; #10
		rinc = 0; 
		
		
		

	end
      
endmodule

